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Altera_Forum's avatar
Altera_Forum
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14 years ago

Signal Assignment Delay

Hi,

I'm working on simulating my project within Altera Quartus 11, using ModelSim Altera. I'm using VHDL code to simulate the design.

I'm giving a signal assignment to one of the inputs, but my reference output on the same channel is roughly taking 6.5ns to update. I would post the waveform and schematic, but being a new member, i'm unable to.

The two signals i'm referring to are mux_vcc (input) and mux_test (output), which are both connected to the same channel. Although in my VHDL code i'm assigning mux_vcc (input) as 0, mux_test (output) is 1 at the very start of the simulation, and only becomes 0 6.5ns into the simulation.

I was wondering if someone would please be able to help me out in removing this delay, as one of the purposes of my circuit is to detect the first 1 bit, and this issue means i'm unable to confirm it's performance.

Any help would be greatly appreciated.

Thanks.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    are you doing a timing/gate level simulation? 6.5ns sounds about right

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    are you doing a timing/gate level simulation? 6.5ns sounds about right

    --- Quote End ---

    Yes, i am doing a gate level simulation, but i was looking for a way in which i could simulate the design without this delay.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    just do an RTL simulation

    --- Quote End ---

    Ok, thanks for the help. I was wondering though, is it possible to do an RTL simulation with VHDL language, as i get this error when attempting this simulation: 

    Info: Start Nativelink Simulation process
Error: NativeLink did not detect any HDL files in the project
Error: NativeLink simulation flow was NOT successful
================The following additional information is provided to help identify the cause of error while running nativelink scripts=================
Nativelink TCL script failed with errorCode:  NONE
Nativelink TCL script failed with errorInfo:  NativeLink did not detect any HDL files in the project
    invoked from within
"if ! {
	    nl_postmsg error "Error: Run Analysis and Elaboration successfully before starting RTL NativeLink Simulation"..."
    (procedure "run_eda_simulation_tool" line 191)
    invoked from within
"run_eda_simulation_tool eda_opts_hash"
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Ignore my last post. I managed to find the solution to this in an old thread. Thanks for the help.