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Altera_Forum
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14 years ago

Signal Assignment Delay

Hi, I'm working on simulating my project within Altera Quartus 11, using ModelSim Altera. I'm using VHDL code to simulate the design. I'm giving a signal assignment to one of the inputs, b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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are you doing a timing/gate level simulation? 6.5ns sounds about right

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Yes, i am doing a gate level simulation, but i was looking for a way in which i could simulate the design without this delay.