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just do an RTL simulation
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Ok, thanks for the help. I was wondering though, is it possible to do an RTL simulation with VHDL language, as i get this error when attempting this simulation:
Info: Start Nativelink Simulation process
Error: NativeLink did not detect any HDL files in the project
Error: NativeLink simulation flow was NOT successful
================The following additional information is provided to help identify the cause of error while running nativelink scripts=================
Nativelink TCL script failed with errorCode: NONE
Nativelink TCL script failed with errorInfo: NativeLink did not detect any HDL files in the project
invoked from within
"if ! {
nl_postmsg error "Error: Run Analysis and Elaboration successfully before starting RTL NativeLink Simulation"..."
(procedure "run_eda_simulation_tool" line 191)
invoked from within
"run_eda_simulation_tool eda_opts_hash"
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