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Altera_Forum
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14 years ago

Signal Assignment Delay

Hi, I'm working on simulating my project within Altera Quartus 11, using ModelSim Altera. I'm using VHDL code to simulate the design. I'm giving a signal assignment to one of the inputs, b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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just do an RTL simulation

--- Quote End ---

Ok, thanks for the help. I was wondering though, is it possible to do an RTL simulation with VHDL language, as i get this error when attempting this simulation: 

Info: Start Nativelink Simulation process
Error: NativeLink did not detect any HDL files in the project
Error: NativeLink simulation flow was NOT successful
================The following additional information is provided to help identify the cause of error while running nativelink scripts=================
Nativelink TCL script failed with errorCode:  NONE
Nativelink TCL script failed with errorInfo:  NativeLink did not detect any HDL files in the project
    invoked from within
"if ! {
	    nl_postmsg error "Error: Run Analysis and Elaboration successfully before starting RTL NativeLink Simulation"..."
    (procedure "run_eda_simulation_tool" line 191)
    invoked from within
"run_eda_simulation_tool eda_opts_hash"