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Altera_Forum
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14 years ago

Signal Assignment Delay

Hi, I'm working on simulating my project within Altera Quartus 11, using ModelSim Altera. I'm using VHDL code to simulate the design. I'm giving a signal assignment to one of the inputs, b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Ignore my last post. I managed to find the solution to this in an old thread. Thanks for the help.