Forum Discussion
2 Replies
- Altera_Forum
Honored Contributor
You can use the tris-state bridge component that connect to the external asyn. SRAM. Both your CPU and IP can now access the external asyn. SRAM through this tri-state bridge. Check the reference design provided under the nios2eds/example directory.
- Altera_Forum
Honored Contributor
many thanks...
Now I try...