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Altera_Forum's avatar
Altera_Forum
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18 years ago

Serial Flash Loader Megafunction (SFL) - how to

Hi,

I want to include SFL Megafunction in my project.

I have created a new project for Cyclone II (EP2C20Q240) and pasted code written by fvm (http://www.alteraforum.com/forum/showthread.php?t=2472&page=2&highlight=sfl+megafunction) (thanks!).


LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY sfl_3c16 IS
END sfl_3c16;
ARCHITECTURE RTL OF sfl_3c16 IS
COMPONENT sfl
  PORT
  (
    noe_in        : IN STD_LOGIC
  );
END COMPONENT;
BEGIN
  sfl_inst : sfl PORT MAP (
  noe_in     => '0'
  );
END RTL;
Of course I have generated sfl using MegaWizard Plug-in Manager.

Next I ran Programmer and configured Cyclone II. After that I click right mouse button on first row and select Attach Flash Device and select EPCS.

Checked Erase checkbox in the EPCS4 row. Unchecked Program/Configure checkbox in FPGA row (because FPGA was configured earlier).

http://urbanowski.pl/error.jpg

I choosed Start and got an error: Flash Loader IP not loaded on device 1. Operation Failed.

What am I doing wrong?

When I choose default SFL (sfl_ep2c20.sof) from quartus\common\devinfo\programmer directory everything works fine! So I think that there is an error in vhdl code or maybe I have not checked any necessary options in quartus (I am a newbie ;)).

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Can you see, that the SFL megafunction has been actually compiled to the configured design? It must be present e. g. in the Quartus hierarchy view. Generally, I experienced some cases, where the SFL wasn't compatible with other design elements (pin usage or I/O voltage assignment) or where it wasn't working correctly, that means not accessing the AS device. But the SFL has been always accessible by the JTAG programmer.

  • Altera_Forum's avatar
    Altera_Forum
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    This design should be basically equivalent to EPC2 factory SFL design.

    Although my example originates from EPC3, I have also used it with

    Cyclone II without problem. There may be a problem, that an unconfigured

    AS memory device is interfering with JTAG. The Quartus programmer

    has an option "Halt on-chip configuration controller" to avoid this situation.

    As a (really trivial) reason, the sof-file selected in Quartus programmer may be

    different from the current compiled design.
  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    There may be a problem, that an unconfigured

    AS memory device is interfering with JTAG. The Quartus programmer

    has an option "Halt on-chip configuration controller" to avoid this situation.

    --- Quote End ---

    OK. But when I am configuring FPGA with "factory default" sfl (quartus/common/devinfo/programmer/sfl_ep2c20.sof) everything is ok and I have access to EPCS4 (without checking option "Halt on-chip configuration controller"). I think there is a "stupid" error in my project. But I will try to enable that option.

    --- Quote Start ---

    As a (really trivial) reason, the sof-file selected in Quartus programmer may be

    different from the current compiled design.

    --- Quote End ---

    No way ;)
  • Altera_Forum's avatar
    Altera_Forum
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    I have no further explanation, except there may be a Quartus V8 problem.

    I did all tests with Quartus V7.2
  • Altera_Forum's avatar
    Altera_Forum
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    I have tried Quartus 7.2 SP3, Quartus 8.0 SP1 and Quartus 8.1 without any success :(

  • Altera_Forum's avatar
    Altera_Forum
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    Hello,

    I have solved my problem. I have checked "Enable INIT_DONE output" and "Enable device-wide output enable (DEV_OE)" [Assignments > Device... > Device and Pin Options > General] and SFL Megafunction is working now :)
  • Altera_Forum's avatar
    Altera_Forum
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    Good, that you succeeded, but strange anyway. I've been using SFL without these pin options. I guess, it's rather

    a problem with AS related pin options. But I remember, that I experienced a mysterious failure of SFL in one

    design. I'll check the effect of pin options ocasionally, when inplementing another design utilizing SFL.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    I guess, it's rather a problem with AS related pin options.

    --- Quote End ---

    You were right. The operation of programming EPCS4 was not sometimes successful with "Enable INIT_DONE output" and "Enable device-wide output enable (DEV_OE)" options checked. So I have been testing other options. I have switched the option "Reserve all unused pins: As output driving ground" to "As input tri-stated" and my design is 100% stable and functional now. Operations of programming, verifing or erasing EPCS4 are always OK.

    "Enable INIT_DONE output" and "Enable device-wide output enable (DEV_OE)" options are not necessary.

    Thank FvM for your help!