SERDES, must be driven by a dedicated clock pin of the PLL

Hello,

the complete message is:

Input clock of PLL which drives at least one nonDPA mode SERDES, must be driven by a dedicated clock pin of the PLL.

My configuration:

- Cyclone V 5CSXFC6D6F31C8NES

- 100 MHz Oscillator which feeds an upstream PLL, which sources the 80 MHz backup clock (and only this clock) for the:

- downstream PLL, which feeds the two SERDES, the main clock (80 MHz) comes from the other board

As I need the possibility to automatically switch over to the backup clock, I cannot directly feed the clock pin into the serdes' PLL, as the clock differences would be too big.

As the upstream PLL has only one output with fanout = 1, I am using a dedicated clock pin of the PLL, so what is the problem? Additionally, nothing else is connected to the oscillator pin.

thanks

http://www.alteraforum.com/forum/showthread.php?t=41837

There is already a thread on the topic, without solution. Can somebody confirm that this is a bug in Quartus 13.0 SP1 which I am using?