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Honored Contributor
Honored ContributorSERDES, must be driven by a dedicated clock pin of the PLL
Hello, the complete message is: Input clock of PLL which drives at least one nonDPA mode SERDES, must be driven by a dedicated clock pin of the PLL. My configuration: - Cyclone ...
Altera_ForumHonored Contributor
Honored ContributorOk, as I have no success in using a PLL cascade, I am now trying to get an oscillator connected.
Because of the HSMC connector, my fractional PLL is restricted to location X0 Y74. How can I use then for example clk4, clk5 or clk0 at this location? The fitter always complains it cannot route the pins. When I use a altclkctrl block, I get the same error as with the cascaded PLL ( dedicated pin blah ... ) Any ideas?
