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Altera_Forum
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14 years ago

Sample synch. signal with unknown phase shift

Hi All,

I have a following problem. I have two devices (Transmitter and receiver). Both devices have a synchronous clock with unknown phase. The distance of the devices is about 300m and they are connected via 192bit wide bus.

The problem is that (according to the spec of the cabling) a delay in each wire is about (4.2+-0.1)ns/m). This means that the signals arrive with different delay and thay have to be realigned.

2nd difficulty is that it is a realtime system and I have about 3 clock cycles to do this and propagate signal to next stages. This means to avoid any complicated fifo.

If I would make it from discrete components I would use a cascade of the buffers in serie and chose the best stage using multiplexer.

I have seen that there is a possibility to modify the delay for the input buffer how ever I need to be able to do this on the fly so for me this is not an option.

the only fpga is in the receicer and it has a stratix I GX fpga

Is there any elegant way how to solve this in altera stratix fpga? reps is there way how to make a cascade of the async delays ??? Or can you recomend some book about async. design in alteras fpga??? I want to avoid putting cascade of D flip flop and program the phase of the sampling frequency.

Thanks a lot for your help !!!

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I would use a phase-compensation FIFO. Since you have no idea what the phase is, they work quite well. You could probably make the offset 2 and have it work fine. Just make sure you release the reset once the clocks are stable. I've attached something I wrote up.

    You could probably do something to detect the latency through and reduce it when it ends up being the high-end, or something like that, but I've never seen anyone do that.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I am not sure. I am programing in VHDL so it will take some time to check verilog file. How ever this solves phase shift of the bus but not the phase shift of the individual bits ?? Do I understand it correctly ???

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Some points are unclear in your specification. What's the data rate and respective skew tolerance?

    What causes the "maximum 3 clock cycles latency" requirement? You have a cable delay of more than 1 us and can't accept another 100 ns?

    If the data rate is 40 MHz, oversampling with a factor of 4 or 8 should be sufficient to correctly align the input data.

    Altera FPGAs have powerful features for skew adjustment of high speed serial interfaces. But they are not available for the large number of inputs.

    Generally I wonder, if a data serialization and a fast, preferably optical medium would allow a simpler design.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Dear Rysc, FvM

    Most of the comments are right but they are exactly the source of my problem. Let's go step by step:

    1) Data rate is clear 40MBd (modulation frequency)* 192 (number of bit)=> 7.68GB and you have to think about them as a group and raw data it is just a vector of the pulses. Also needed skew is 0 I have to identify the pulse with one clock cycle precision.

    2) the problem of the optical fiber (which we have in parallel) is that delay is about 5ns/m also serialisation and deserialisation takes some time and I have a limited time when I have to receive the information. With the optics I am a few clock cycles late for several cases of the applycation. This also gives the answer about limited number of the clock cycles. I have to do some calculations too and I really dont have much time.

    3) I have also problem if I kick the D flip flop and I put it metastable state for a few clock cycles this can generate extreme problem if it happens often.

    This is why I have put this post here. I am thinking about it and I don't have much options. If you are interrested in more details I can send you an email to explain the project.

    so the problem is clear I have to be fast and prevent met. state