S10 programming file conversion

I was able to try a few more Quartus version today and I am able to get the board to boot with a sof generated with 24.1 if I create the jic using 20.3.

Here a summary of what I've tried:

I should reiterate that this is not the S10 development board. The GHRD files I have from Terasic are from Quartus 19.4. The other sof versions in the table I compiled after updating from the 19.4 version.

The 2019.04 u-boot is the one provided by Terasic with the board. The 2024.07 u-boot is compiled from the altera-opensource/u-boot-socfpga github at QPDS24.2_REL_GSRD_PR tag, following the steps for the S10 development board, except using the device tree provided by Terasic.

This appears to be related to quartus_pfg version used, as the boot results are the same regardless of u-boot version. I would think that the generate jic file should function essentially the same regardless of the Quartus version used. Maybe newer version have changes to the SDM control timing that is causing this issue?

On top of the new Quartus version, I've also tried switching to HPS first booting (board GHRD is FPGA first). I'm doing this with the 24.1 sof and creating the jic/rbf with 24.1 as well (which always fails boot with FPGA first). Now when it boots, it sometimes resets itself where it was hanging with FPGA first and then boots successfully:

U-Boot SPL 2024.07-36773-g0dad0a0a478-dirty (Mar 18 2025 - 15:06:18 -0400)
Reset state: Cold
MPU         1200000 kHz
L3 main     400000 kHz
Main VCO    2400000 kHz
Per VCO     2000000 kHz
EOSC1       25000 kHz
HPS MMC     50000 kHz
UART        100000 kHz
<Sometimes hangs here indefinitely, sometime hangs here for a few seconds and continues to below>

U-Boot SPL 2024.07-36773-g0dad0a0a478-dirty (Mar 18 2025 - 15:06:18 -0400)
Reset state: Cold
MPU         1200000 kHz
L3 main     400000 kHz
Main VCO    2400000 kHz
Per VCO     2000000 kHz
EOSC1       25000 kHz
HPS MMC     50000 kHz
UART        100000 kHz
DDR: 32768 MiB
SDRAM-ECC: Initialized success with 7879 ms
QSPI: Reference clock at 400000 kHz
... <boots succesfully if it makes it to here>

It almost always hangs indefinitely when the board has been off for more than 30 seconds, and it resets itself and boots successfully about 70% of the time if I power cycle the board quickly.

If I do the HPS first booting and use 20.3 to create the jic/rbf then it boots normally (no restart of the SPL during boot). This seems to indicate the timing of the boot is different with jic files generated with newer Quartus versions. Maybe the SDM is loading faster and DDR4 is not ready or something like that. Is there a way to delay u-boot at power up?

I have tried the latest combination of u-boot and quartus release listed in the link above. My problem is that this only works for this board if I use PFG from 20.3 to create the jic file.

The jic output from this command does not boot:

c:\intelFpga\24.3\quartus\quartus_pfg -c test.sof output.jic -o device=MT25QU01G -o flash_loader=1SX280HU2F50E1VG -o hps_path=u-boot-spl-dtb.hex -o mode=ASX4

But the jic output from this command does boot:

c:\intelFpga\20.3\quartus\quartus_pfg -c test.sof output.jic -o device=MT25QU01G -o flash_loader=1SX280HU2F50E1VG -o hps_path=u-boot-spl-dtb.hex -o mode=ASX4

The link you provided lists fixes that were done to u-boot and the ghrd, but says nothing about quartus_pfg and what different version do differently when generating a jic from the exact same input files. This seem somewhat import considering the recommendation that we should be using the latest PFG version to convert files even if they are generated with older versions of Quartus (https://www.intel.com/content/www/us/en/docs/programmable/683762/23-1/updating-the-sdm-firmware.htm).