Honored ContributorI'm planning to use the ALT_GX module in an Arria II GX FPGA like indicated here:
http://www.altera.com/literature/an/an610.pdf Page 7, figure 4. The question I have is which output pin should I route the rx_clkout to to feed the clean up PLL? Can it be any I/O pin, or should it be a pll#_clkout pin? Thank you
Honored ContributorAllow Quartus to be your guide; P&R a design using a regular I/O and then again using a PLL_OUT pin.
I suspect that you will get a warning regarding excess jitter when you use a regular I/O pin. That is the type of warning you get when driving a PLL clock output to a non PLL-out pin. Cheers, DaveHonored ContributorI'll will examine what Quartus does, but it seems curious that the PLL_OUT pin can only be pseudo-differential, but if I use a regular out pin, I can drive the pins in true differential, like LVDS. Either way, if I am using this signal to feed a clock jitter cleaner chip, it seems like I will suffer (either because I am not using a clock chip, or because I'm not driving in true differential style).
Therefore, which is the better way to go? Seeing that http://www.altera.com/literature/an/an610.pdf Page 7, figure 4. Suggests to do this, what is the suggested pin type to use? Thank youHonored Contributor
