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Altera_Forum
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13 years ago

rx_clkout - route to which output pin

I'm planning to use the ALT_GX module in an Arria II GX FPGA like indicated here: http://www.altera.com/literature/an/an610.pdf Page 7, figure 4. The question I have is which output pin sho...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Allow Quartus to be your guide; P&R a design using a regular I/O and then again using a PLL_OUT pin.

I suspect that you will get a warning regarding excess jitter when you use a regular I/O pin. That is the type of warning you get when driving a PLL clock output to a non PLL-out pin.

Cheers,

Dave