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Honored Contributor
Honored ContributorRMII Mode Selection / Strapping CYCLONE III
Hi,
I am working in ALTERA CYCLONE III . I have designed a module with the following NIOS II Processor + Custom Ethernet MAC working in RMII Mode + SSRAM. The Ethernet PHY used in this FPGA is DP83848C. Since I am working with a custom Ethernet MAC with RMII Mode , I have to configure the PHY to RMII. Referring the Spec of DP83848C PHY,we can select RMII mode by strapping mechanism.To do so , RX_DV/MII_MODE pin of DP83848C has to connected to VCC through a external 2.2K ohm Resistor.Whether we can configure some registers to make this selection in the CYCLONE III or we have make some external connections ? Please Note : See the Attached PHY Document17 Replies
Altera_ForumI did, but unfortunately I can't share the code. IIRC it wasn't that hard to do. I suggest to use signaltap on your conversion component to see what happens.
And I'm sorry, I don't understand Chinese.- Altera_Forum
Dear daixiwen:
thank you for your reply,and I have some problems to: I can't ping the board,and I used the signaltap to test the mdio and phy_RXD(you can get info from attachments),the signatap process always waiting for trigger,did I miss sth? here is the nios debug detail: Running... INFO : TSE MAC 0 found at address 0x00002000 INFO : PHY National DP83640 found at PHY address 0x01 of MAC Group[0] INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0] INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link... INFO : PHY[0.0] - Auto-Negotiation PASSED INFO : PHY[0.0] - Checking link... INFO : PHY[0.0] - Link established INFO : PHY[0.0] - Speed = 1000, Duplex = Full Waiting for link...OK IP address: 219.245.66.185 IP netmask: 255.255.255.0 IP gateway: 219.245.66.254 UDP Dest IP address: 219.245.66.112 OK. waiting for your reply,thank you! - Altera_Forum
What are you triggering on?
What is the phy_rx_err signal and what is it connected to on the PHY side? If it is the combined rx enable/error, I find it strange that it isn't asserted when you see changes on the RX[0] and RX[1] signals... it could be a bad connection to the PHY. - Altera_Forum
Dear Daixiwen:
For many days passed,my problem still going on,I use the LWIP+TSE+DP83640+rmii to do the project! Here is my board information, I use the example from the forum, the webside http://www.alteraforum.com/forum/showthread.php?t=23787 trying to ping the board,I get the information: Running... INFO : TSE MAC 0 found at address 0x00004000 INFO : PHY National DP83640 found at PHY address 0x01 of MAC Group[0] INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0] INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link... INFO : PHY[0.0] - Auto-Negotiation PASSED INFO : PHY[0.0] - Checking link... INFO : PHY[0.0] - Link established INFO : PHY[0.0] - Speed = 1000, Duplex = Full Waiting for link...OK Waiting for DHCP IP address...@����������������������������������������������� can't get the DHCP IP address,I debug step by step,I found my software jump to this line if(ethernetif->lwipRxCount == 0) return NULL; in function low_level_input(struct netif *netif). the mdio detect correctly also the mac rx_clk tx_clk,but rxd and txd t detect anything ! the attachment is my board information,maybe you can give me some help! best wishes to you,thank you! - Altera_Forum
Did you check my questions?
- Altera_Forum
yeah,my phy can work on rmii module,the phy_rx_err signal combined rx enable/error,but I'm not sure my rmii to mii interface work normally！
- Altera_Forum
Did you try to trigger on the combined rx enable/error signal? If this signal never goes to 1 then the problem isn't in the rmii to mii interface, but before that. Either the PHY isn't connected correctly to the FPGA, or the PHY itself doesn't receive anything, is badly configured or broken.
