Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

RMII Mode Selection / Strapping CYCLONE III

Hi, I am working in ALTERA CYCLONE III . I have designed a module with the following NIOS II Processor + Custom Ethernet MAC working in RMII Mode + SSRAM. The Ethernet PHY used in this FPGA i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Did you try to trigger on the combined rx enable/error signal? If this signal never goes to 1 then the problem isn't in the rmii to mii interface, but before that. Either the PHY isn't connected correctly to the FPGA, or the PHY itself doesn't receive anything, is badly configured or broken.