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Altera_Forum
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16 years ago

RMII Mode Selection / Strapping CYCLONE III

Hi, I am working in ALTERA CYCLONE III . I have designed a module with the following NIOS II Processor + Custom Ethernet MAC working in RMII Mode + SSRAM. The Ethernet PHY used in this FPGA i...
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Altera_Forum
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12 years ago

What are you triggering on?

What is the phy_rx_err signal and what is it connected to on the PHY side? If it is the combined rx enable/error, I find it strange that it isn't asserted when you see changes on the RX[0] and RX[1] signals... it could be a bad connection to the PHY.