Resetting FPGA before clock starts

I speak mostly Verilog, mostly, so my apologies if you speak VHDL:

/* The initialization below will be present after configuration */

reg sync[2:0] = 3'b000;

always @(posedge clk) sync <= {sync[1:0],1'b1};

/* if you want reset_n to stay low for more clocks, init a counter with sync[2] */

assign reset_n = sync[2];

I am using Verilog and SystemVerilog. Yes, I have done something like what you suggest and it does seem to work. I just got my first FPGA hardware design back this afternoon and I was trying to turn it on. Lots of things I had never done before, like the serial flash memory for configuration, and using an external programmer to dump the configuration into the flash. It was the first time I had designed and laid out that hardware and I didn't yet know how I could do a very simple test to see if it worked.

But I did try a reset register and set it to a starting value like you suggested and used it to load a register that drives some status LEDs. And it all turned on as I expected, first time - WOW!

Of course, my question was not so much how to maintain a reset for some number of clocks, but how to initialize a bunch of different registers in my design before ANY clocks have yet happened. It seems to work in the simple case I tried with the status LEDs, but I will need to apply it further to set all my outputs to a known initial state.

Hmm. Having difficulty understanding exactly what you want to do. But let's assume you've got 3 registers: reg_a, reg_b, and reg_c. They connect to your FPGA's outputs. Then, using the reset_n signal above, asynchronously reset them:

always @(posedge clk or negedge reset_n) begin
  if (!reset_n) begin
    /* regs will take on these values before the first rising edge of clk */
    reg_a <= 1'b0; reg_b <= 1'b1; reg_c <= 1'b0;
  end
  else begin
    /* "normal" next values for rising edge of clk */
  end
end

Alternatively, you could initialize all of them the way I initialized sync[2:0] above.

If this still isn't what you're after, perhaps read about the DEV_CLRn pin in the Cyclone III handbook.