Resetting FPGA before clock starts

I am using Verilog and SystemVerilog. Yes, I have done something like what you suggest and it does seem to work. I just got my first FPGA hardware design back this afternoon and I was trying to turn it on. Lots of things I had never done before, like the serial flash memory for configuration, and using an external programmer to dump the configuration into the flash. It was the first time I had designed and laid out that hardware and I didn't yet know how I could do a very simple test to see if it worked.

But I did try a reset register and set it to a starting value like you suggested and used it to load a register that drives some status LEDs. And it all turned on as I expected, first time - WOW!

Of course, my question was not so much how to maintain a reset for some number of clocks, but how to initialize a bunch of different registers in my design before ANY clocks have yet happened. It seems to work in the simple case I tried with the status LEDs, but I will need to apply it further to set all my outputs to a known initial state.