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Altera_Forum's avatar
Altera_Forum
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14 years ago

Resetting FPGA before clock starts

Is there any way to initialize a Cyclone III FPGA after it has read its configuration but before the external clock starts up? My overall design uses a CPU which has to boot up and eventually I will ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hmm. Having difficulty understanding exactly what you want to do. But let's assume you've got 3 registers: reg_a, reg_b, and reg_c. They connect to your FPGA's outputs. Then, using the reset_n signal above, asynchronously reset them: 

always @(posedge clk or negedge reset_n) begin
  if (!reset_n) begin
    /* regs will take on these values before the first rising edge of clk */
    reg_a <= 1'b0; reg_b <= 1'b1; reg_c <= 1'b0;
  end
  else begin
    /* "normal" next values for rising edge of clk */
  end
end

Alternatively, you could initialize all of them the way I initialized sync[2:0] above.

If this still isn't what you're after, perhaps read about the DEV_CLRn pin in the Cyclone III handbook.