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Altera_Forum's avatar
Altera_Forum
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13 years ago

Resetting FPGA before clock starts

Is there any way to initialize a Cyclone III FPGA after it has read its configuration but before the external clock starts up? My overall design uses a CPU which has to boot up and eventually I will ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I speak mostly Verilog, mostly, so my apologies if you speak VHDL:

/* The initialization below will be present after configuration */

reg sync[2:0] = 3'b000;

always @(posedge clk) sync <= {sync[1:0],1'b1};

/* if you want reset_n to stay low for more clocks, init a counter with sync[2] */

assign reset_n = sync[2];