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Altera_Forum
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12 years ago

Regarding PLL_CLKOUTp & PLL_CLKOUTn pins in Cyclone FPGA -IV E series

Dear sir,

I am new to fpga programming. I want to know where & how do we configure PLL_CLKOUTx pin as a

a. Dedicated PLL clock output

b. General I/O

Regards,

Thulasi

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    To use the pin as general I/O use Quartus' pin planner to assign the pin to a signal in your design. Depending on the I/O standard you require you will be able to use both PLL_CLKOUTp & PLL_CLKOUTn pins independently for single ended I/O standards. If using a differential I/O standard you will only be able to assign a signal to PLL_CLKOUTp. PLL_CLKOUTn will automatically be assigned.

    To use as a dedicated PLL clock output you will need to instantiate a PLL in your design. I recommend you use Quartus' MegaWizard to create the PLL. Once you have put this in your design you will, again, be able to use the pin planner to assign the required pin to an output of the PLL.
  • Altera_Forum's avatar
    Altera_Forum
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    Dear Sir,

    Thanks a lot. Now, in connection guildelines of Cyclone-IV, it is mentioned as "When not using this pin as a clock output, this pin may be used as a user I/O. When not using these pins, connect them as defined in Quartus II software. "

    What is the recommended option that needs to be selected for this type of unused pins in Quartus software?

    The following are the available options.

    As bidirectional

    As input tri-stated

    As o/p driving an unspecified signal

    As output driving ground

    As o/p driving VCC and so on...

    Please help.

    Regards,

    Thulasi
  • Altera_Forum's avatar
    Altera_Forum
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    This very much depends on your requirements. There are options for good reason. There is no wrong answer, you only risk incompatibility with external circuitry.

    My latest project has left the setting as 'input tri-stated with weak pullup'. This is the default for Cyclone IV and I rarely change this. This allows you to connect signals to the pins should you wish to use them later. Provisioning them to be inputs is fairly risk free, just ensure nothing on your board can overdrive them.

    If you particularly wish to minimise noise in your system you can chose to set then as outputs driving to ground and connect all those unused pins to ground on your PCB.

    Once your FPGA design has been generated refer to the {project_name}.pin file. This identifies how Quartus is expecting every pin on your chosen device to be connected. Unused pins will reflect the earlier choice you made. Pay attention to the 'GND+' pins. Cyclone devices may not behave correctly if these unused clock inputs are not grounded, or driven, on your board - although I have never seen any evidence of this, despite having captured boards with these pins left floating.

    Regards,

    Alex