Regarding PLL_CLKOUTp & PLL_CLKOUTn pins in Cyclone FPGA -IV E series

This very much depends on your requirements. There are options for good reason. There is no wrong answer, you only risk incompatibility with external circuitry.

My latest project has left the setting as 'input tri-stated with weak pullup'. This is the default for Cyclone IV and I rarely change this. This allows you to connect signals to the pins should you wish to use them later. Provisioning them to be inputs is fairly risk free, just ensure nothing on your board can overdrive them.

If you particularly wish to minimise noise in your system you can chose to set then as outputs driving to ground and connect all those unused pins to ground on your PCB.

Once your FPGA design has been generated refer to the {project_name}.pin file. This identifies how Quartus is expecting every pin on your chosen device to be connected. Unused pins will reflect the earlier choice you made. Pay attention to the 'GND+' pins. Cyclone devices may not behave correctly if these unused clock inputs are not grounded, or driven, on your board - although I have never seen any evidence of this, despite having captured boards with these pins left floating.

Regards,

Alex