Honored Contributorhi
1.in my design using cyclone3 critical warning "RULE D101 is violated "is coming 2. but my design is working properly, there is any problem if i proceed with critical warning regards
Honored ContributorThis is a severe violation of general design rules!
You didn't synchronize bits between clock domains, this causes often metastability issues and the weirdest behavior in target implementations. Maybe it isn't so severe in your special case if you derived both clockdomains from the same PLL and the frequencies are harmonics. But nevertheless use dual rank synchronizers between clockdomains! A good read for that: Chapter 5: Design Recommendations for Altera Devices and the Quartus IIHonored Contributorhi ruschi!
thanks for your reply, can you tell me how to use" dual rank synchronizers between clockdomains!" regrads mkrajHonored ContributorHello mkraj33, your design may work temporarily, but a long run it may fail. You can do a long run check and verify still the logic works. If you are using dual clocks it is always a good practice to synchronize between clock domains otherwise you will end up with unpredictable results.
Honored Contributorhi
can any one explain how to avoid the metastability problem by using dualrank synchronizers regards mkrajHonored Contributoryes, just read the chapter that ruschi (http://www.alteraforum.com/forum/member.php?u=8546) recomended
