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Honored Contributor
Honored Contributorreg critical warning
hi 1.in my design using cyclone3 critical warning "RULE D101 is violated "is coming 2. but my design is working properly, there is any problem if i proceed with critical warning regards
Altera_ForumHonored Contributor
Honored ContributorThis is a severe violation of general design rules!
You didn't synchronize bits between clock domains, this causes often metastability issues and the weirdest behavior in target implementations. Maybe it isn't so severe in your special case if you derived both clockdomains from the same PLL and the frequencies are harmonics. But nevertheless use dual rank synchronizers between clockdomains! A good read for that: Chapter 5: Design Recommendations for Altera Devices and the Quartus II
