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xingyunzhidi's avatar
xingyunzhidi
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7 months ago

The issue encountered during testing after programming the R-tile PCIe DMA Design Example on the Agi

I followed the instructions in section 3.5 of the Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example User Guide for configuration, but encountered issues during testing. Below are the c...
Board Debug
VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
7 months ago

Hi @xingyunzhidi,


Thanks for reaching out.


I want to replicate it on my end. Please share the following items:

1. The .ip file that you used to generate the R-Tile MCDMA Design Example.

2. Quartus version used.


Thanks.

Best Regards,

Ven


xingyunzhidi's avatar
xingyunzhidi
Icon for New Contributor rankNew Contributor
7 months ago

Hello, my issue has been resolved, and I can now perform the DMA test normally. However, I’m a bit confused by the results. When testing with small data sizes (a few tens of KB), the measured bandwidth is less than 1GB/s. I also noticed that the test results in the Design Example User Guide are similar. What could be causing this? Also, is it possible to change the Qdepth value? If so, how can I modify it? Thanks!