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Arnab1's avatar
Arnab1
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2 years ago

Stratix 10 MCDMA host: Queue reset failed

Hello, I have been trying to get an MCDMA example design working on a Stratix 10 MX device (1SM21BEU2F55E2VG). You can consider me a beginner with the Intel FPGAs. The project details are a...
Board Debug
Configuration
Fpga Devkit
Generic Io
Other Ips
VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi @Arnab1,


Thanks for reaching out to us.


May I know which MCDMA Avalon-MM DMA Design Example and driver you are using? With SRIOV support enabled? There are multiple of MCDMA Design Examples, and each variant of the MCDMA design example is supported by specific driver only. Please make sure that the driver used is appropriate.


Can you please make sure the prerequisites and software setup for the selected driver are performed according to the steps outlined in the User Guide?


Next, what are the test programs you performed from the User Guide? It would be helpful if you could screenshot the commands you entered and errors you encountered to help us better narrow down the issue.


Regarding the host side (lspci_output.png), the link speed appears to be downgraded from (Gen 3) 8 GT/s to 2.5 GT/s. Can you please check if the host PCIe settings are able to support Gen 3?


Thanks.

Best Regards,

VenTingT


Arnab1's avatar
Arnab1
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2 years ago

Dear VenTingT,

Thank you for your reply. I am providing the information below that you have requested for. I have also attached the screenshots of relevant configuration/outputs that could provide more insight into the issue.

I am using "H-Tile Multichannel DMA Intel FPGA IP for PCI Express" on Stratix 10 MX device (1SM21BEU2F55E2VG). I generated the example design simply by clicking on the "Generate Example Design" button, which generated the Quartus project files (named pcie_ed.qar) and the software codes containing the kernel and user codes. You can find all IP configuration details in the screenshots.

SRIOV was disabled. I wanted to have a bare minimum working MCDMA - AVMM design.

I understand. In this case, I was using the kernel+user code that was generated along with the Quartus example design files (present in the software directory).

I followed the steps that are mentioned here - https://www.intel.com/content/www/us/en/docs/programmable/683517/23-4/quick-start-guide.html

I followed this for the BIOS configuration + setting up hugepages + loading uio + compiling and loading ifc_uio driver process, and I did not see any error here.

For the tests, I started with the devmem utility and simple_app examples. I have attached the screenshots. However, not much debug info/error info is available, and there is nothing in the kernel log too. Same goes for the examples too.

I noticed that, but chose to continue despite that. The server supports PCIe Gen3 (and Gen4 too), and the link configuration is set to automatic. If needed, I can fix that to Gen3; let me know.

Let me know if you need any further information in this regard. Thanks!

Kind regards,
Arnab

  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi @Arnab1,

    Thank you for attaching the screenshots.

    May I know are you using the MCDMA custom driver?

    Besides, for the devmem utility, are you trying to perform the IP reset as in the Step 4. of Section 3.5.2.3.3.? The command you entered seems different from the one specified in the IP reset step.

    It is suggested to change the host PCIe support to Gen3 which follows the design. Could you try to perform the tests again after the changes made?

    Thanks.

    Best Regards,

    VenTingT