SDRAM without HPS

Hello. I apologize for the late reply. At the moment @sstrell was right about the sdc and and my lack of pin assignment. I was finally able to see the signals i wanted in signal tap after putting in pre synthesis.

Currently I am able to see some sort of correct semblance on the waveform but for some reason it is not quite right.

I am certain it is my finite state machine code or something but I am still trying to find the problem functionally.

I wanted to see if I can get the waveform right before posting it.

I think my next problem is regarding SDRAM wait request.

I coded it the address/data to latch when it is high and only change the data/address when it is low as suggested,.

On the other hand I cant predict when SDRAM will be high or not.

Is this something completely random or is there some kind of timing it follows so we can predict when SDRAM wait request will be low.

At the moment, I see this SDRAM wait request as some annoying enable signal. I wonder if this is completely natural in the memory interface.

Is it alright if I can work on it a bit longer before following up?

I apologize again for the delay.

But Thank you for the replies.

-htolentino