Schematics/layout for TerasIC SoCKit rev. D with Cyclone V

Quick update. Perhaps this could be useful to someone in the future.

I tried some hacks to move the project forward, such as using VGA's V/H sync pins as I/O [only VGA_VS works for some reason], tracing connections on the PCB [while many of these traces are easily visible & trackable on the bottom layer, turns out you cannot use dedicated differential SERDES I/O as GPIO on Cyclone V]... Also trying to mix and match schematics for HTG-SMC HCSM adapter [there is a terasIC's tool called SystemBuilder, which actually runs under WINE, to generate a Quartus project, including pinout for this adapter -- but is ultimately incorrect for my board], and schematics for Altera HSMC debug header (which actually has the correct connector). I did not succeed so far in actually mapping enough HSMC generic I/O pins to pads on the chip for my needs. I can keep trying, and I will win... but this wastes so much time. Wish there were schematics: the effort would be reduced 100x.

FWIW, I do not wish to solder to the pushbuttons or switches (4 of each on the FPGA [not CPU] side), because I/O impedances matter, plus the board has been loaned to me -- so I dare not solder to FPGA's pads on the bottom layer (which conveniently appear to be via-in-pad).