Mac internal loopback F-Tile, Quartus 25.2

Hi thank you for quick response,

My intent is to test only internal loopback, I want to drive single frame on Tx MAC AVST protocol and receive single frame on Rx AVST protocol. I do not want to use external loopback. I have performed test with my Reflexv2 board according to F-Tile Ethernet Intel FPGA Hard IP 23.4 Design Example User Guide. I successfully generated project and ported it to Reflexv2. However when I performed run test script to test internal loopback I had a problem. Test has returned that pcs ready signal has not established.

I slightly modified this project, added my reset sequence, and performed successfully loopback, but I needed to:

Enable PCS TX RX Loopback inside IP MAC. Connect qsfp dd cable that is split for 2x qsfp into E810 card.

Then I have observed that pcs ready has been established. I have received TX Ready on AVST and I was able to send and receive single frame on RX AVST interface. And here is my concern. Is that possible to do it without connection to external card? Otherwise pcs ready is low and I do not see TX Ready signal on AVST interface.

Best Regards, Przemyslaw