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Vigneswaran's avatar
Vigneswaran
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5 days ago

LVDS support on Agilex 7

HI, Im working on INTEL AGILEX 7 F-SERIES X2 F-TILE FPGA.  Please clear my doubt   In True differential signalling of LVDS , it is mentioned as differential signal with common mode voltage of 1.4 y...
Configuration
Core Logic
Programmable Logic Device
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 days ago

Hi Vigneswaran,

I think, you don't need additional margin for datasheet specifications of maximal Vicm and Vid. We can assume that the specificatons are well considered. Possible exeedance during power on should be however avoided. I'd assume that unterminated LVDS driver can have a least doubled voltage swing, worst case up to supply rails. If this is critical, you should use external instead of programmed internal termination. 

Regarding ZL30733 usage on Altera Development Kits, I can't determine if it keeps maximum Agilex 7 ratings, I don't have a device datasheet. According to product brief, output Vocm is programmable and has factory configurable power-on configuration. So it might use safe parameters. Said device kit is however using VDD of 1.2V for GPIO banks containing respective TDS clock inputs, thus limits are lower than discussed for 1.5V TDS.

Regards
Frank