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Gonza's avatar
Gonza
Icon for New Contributor rankNew Contributor
1 month ago
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Agilex 5 FPGA EMIF: sharing LPDDR4 reference clock between Bank 3A and Bank 3B

Hello, I'm working with an Agilex 5 E-Series A5ED043BB32AI4S device. On my board, I have two 32-bit LPDDR4 interfaces connected to the HSIO banks 3A and 3B. The DDR reference clock is available only...
Core Logic
Programmable Logic Device
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    29 days ago

    Hi Gonza​ , 

    1. For the FPGA LPDDR4 External Memory Interfaces (EMIF) IP, is it mandatory that the PLL reference clock be located in the same bank as the EMIF instance?
      1. We recommended to have the refclk placed within the Address and Command Group of each interface.
      2. While sharing PLL reference clock within an IO Bank is still permitted.
    2. Is there any supported mechanism to share or bypass the PLL reference clock from the EMIF PLL in bank 3A to the EMIF PLL in bank 3B, similar to what appears to be done automatically by the HPS EMIF 2x32 implementation?
      1. You can use clock bridge IP to supply the clock to both EMIF interfaces across the banks.
      2. If you still facing the issue, please share the example design for debugging purpose.

     

    Regards,

    Adzim

AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
29 days ago

Hi Gonza​ , 

  1. For the FPGA LPDDR4 External Memory Interfaces (EMIF) IP, is it mandatory that the PLL reference clock be located in the same bank as the EMIF instance?
    1. We recommended to have the refclk placed within the Address and Command Group of each interface.
    2. While sharing PLL reference clock within an IO Bank is still permitted.
  2. Is there any supported mechanism to share or bypass the PLL reference clock from the EMIF PLL in bank 3A to the EMIF PLL in bank 3B, similar to what appears to be done automatically by the HPS EMIF 2x32 implementation?
    1. You can use clock bridge IP to supply the clock to both EMIF interfaces across the banks.
    2. If you still facing the issue, please share the example design for debugging purpose.

 

Regards,

Adzim

  • Gonza's avatar
    Gonza
    Icon for New Contributor rankNew Contributor
    29 days ago

    Hi ADzim,

    Thank you for your suggestion.

    The Clock Bridge IP solution works in my case. I am now able to instantiate and fit two LPDDR4 FPGA EMIF instances (one in bank 3A and one in bank 3B) using a single reference clock source located in bank 3A.