8 port 10/25G ethernet interface in Stratix 10

Testing with a Fixed Ethernet Packet (Port-to-Port / Loopback)

The quickest path is the E-Tile Hard IP for Ethernet hardware design example, which includes a built-in packet generator and checker. The hardware design example includes the E-Tile Hard IP for Ethernet IP core plus a PCS packet generator and checker that coordinates IP core programming, packet generation, and packet verification. 100GE PCS with Optional RS-FEC Hardware Design Example Components

After compiling and programming the device via JTAG, you drive it through the Quartus Prime System Console using a Tcl script. The key commands you'll use are:

start_pkt_gen — starts the packet generator; stop_pkt_gen — stops it. 100GE MAC+PCS with Optional (528,514) RS-FEC or (544,514) RS-FEC and Adaptation Flow Hardware Design Example

chkphy_status — displays clock frequencies and PHY lock status; chkmac_stats — displays MAC statistics counter values; clear_all_stats — clears the statistics counters. 100GE MAC+PCS with Optional (528,514) RS-FEC or (544,514) RS-FEC and Adaptation Flow Hardware Design Example

loop_on — turns on internal serial loopback; loop_off — turns it off. 100GE MAC+PCS with Optional (528,514) RS-FEC or (544,514) RS-FEC and Adaptation Flow Hardware Design Example

To configure the packet generator for a fixed-size packet, use these registers:

0x1008 (Packet Size Configure) — bits [10:0] specify the transmit packet size in bytes. 10GE/25GE Design Examples Registers

0x1009 (Packet Number Control) — specifies the number of packets to transmit from the packet generator (HW reset value = 0xA). E-Tile Hard IP Intel® Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

0x1010 (PKT_GEN_TX_CTRL) — bit [1] is the packet generator disable bit (write 1 to turn off, 0 to turn on); bits [5:4] = 01 selects fixed mode; bit [6] = 1 enables using register 0x1009 to stop the generator after a fixed packet count. E-Tile Hard IP Intel® Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

Switching Between 10G and 25G Rates (Dynamic Reconfiguration)

The 10G/25G Ethernet Dynamic Reconfiguration design example demonstrates a dynamic reconfiguration solution for Stratix 10 devices using the E-Tile Hard IP for Ethernet IP core, supporting variants including 25GE with RS-FEC and PTP, 25GE, 10GE, and 1GE. 10G/25G Ethernet Dynamic Reconfiguration Design Examples

The high-level procedure for each rate switch transition is:

Assert (toggle) the sl_tx_rst_n and sl_rx_rst_n reset signals. 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components

Disable SERDES using PMA attribute code 0x0001. 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components

Trigger PMA analog reset. 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components

Change the transceiver TX bit/refclk ratio to the destination rate (refclk = 156.25 MHz), then change the transceiver RX bit/refclk ratio to the destination rate (refclk = 156.25 MHz). 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components

Reconfigure the registers for the Ethernet, RS-FEC, and transceiver blocks — the details of the changed register values are in the c3_reconfig.c file generated with the design example. 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components

Adjust the phase offset of the recovered clock using PMA attribute code 0x000E. 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components

Re-enable SERDES using PMA attribute code 0x0001. 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components

Deassert sl_tx_rst_n and sl_rx_rst_n, then for 10G/25G DR transitions wait for PIO_OUT[4:0] = 0x1F (o_sl_tx_ptp_ready, o_sl_rx_pcs_ready, o_tx_pll_locked, o_sl_tx_lanes_stable, o_sl_rx_ready, o_sl_ehip_ready all asserted). 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components