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shxb's avatar
shxb
Icon for New Contributor rankNew Contributor
4 years ago

RAM to DSP

hi,

we have data path : RAM output->normal_reg->DSP_input_reg ,

there is only one "normal_reg" , but it drives 8 DSPs, timing violation path reported for "RAM output->normal_reg".

without insert clock cycles , what can we do to fix it?

maybe move the "DSP_input_reg" outside DSP block helps? i do not know how to constrains it on RTL, or some other suggestions?

thanks

2 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    Enable register duplication to break up the fanout of normal_reg.

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    Hi @shxb

    May I know the suggestion from sstrell helps?

    Best Regards,
    Richard Tan

    p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.