shxb
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RAM to DSP
hi, we have data path : RAM output->normal_reg->DSP_input_reg , there is only one "normal_reg" , but it drives 8 DSPs, timing violation path reported for "RAM output->normal_reg". without insert clock cycles , what can we do to fix it? maybe move the "DSP_input_reg" outside DSP block helps? i do not know how to constrains it on RTL, or some other suggestions? thanks792Views0likes2Commentstiming constraints
hi, We have encountered timing failure in Quartus, it is due to massive RAM usage, above 90 percent, we do not pipeline enough cycles for control signals, and without implementing modification in RTL, because it related so many modules. Can we set some constraints in synthesis or PR stage to solve this problem? eg: max fanout? Does this synth_attribute have module level syntax? or any other suggestion ? TCL command is preferred, thanks in advance.1.3KViews0likes4Comments