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shxb's avatar
shxb
Icon for New Contributor rankNew Contributor
4 years ago

timing constraints

hi,

We have encountered timing failure in Quartus, it is due to massive RAM usage, above 90 percent, we do not pipeline enough cycles for control signals, and without implementing modification in RTL, because it related so many modules.

Can we set some constraints in synthesis or PR stage to solve this problem? eg: max fanout? Does this synth_attribute have module level syntax? or any other suggestion ? TCL command is preferred, thanks in advance.

4 Replies

  • SyafieqS's avatar
    SyafieqS
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    Shen,


    Quartus has few syn attribute in file->new file-> right click insert template_> Quartus attribute. I believe the attribute you are looking for might be there, fanout etc. Might need to check on this first.


  • shxb's avatar
    shxb
    Icon for New Contributor rankNew Contributor
    4 years ago

    i am sorry it does not help. i want to do project level constraint, not module level constraint, for it has so many related modules.

  • SyafieqS's avatar
    SyafieqS
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    Hey,


    I might misunderstand the description earlier as this due to timing failure. If the RAM is due to high fanout, without modifying the RTL, there is Quartus tool can duplicate register in assignment editor. You can specify the node and manual duplication register and value of how much register need to be replicated. The tool will handle the placement and routing. Or, you try to over constraint the node to see if Quartus can pull the register closer by specifying set_max_delay.