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shxb's avatar
shxb
Icon for New Contributor rankNew Contributor
5 years ago

timing constraints

hi, We have encountered timing failure in Quartus, it is due to massive RAM usage, above 90 percent, we do not pipeline enough cycles for control signals, and without implementing modification in...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
4 years ago

Hey,


I might misunderstand the description earlier as this due to timing failure. If the RAM is due to high fanout, without modifying the RTL, there is Quartus tool can duplicate register in assignment editor. You can specify the node and manual duplication register and value of how much register need to be replicated. The tool will handle the placement and routing. Or, you try to over constraint the node to see if Quartus can pull the register closer by specifying set_max_delay.