Question Regarding LVDS SERDES Receiver Clock Requirements in Agilex 7 F-Series

I apologize for the unclear explanation. Please allow me to explain my concerns more clearly.

I’m assuming a circuit configuration as shown below:

I would like to ask about the following two points:

1. Requirement for tREFPJ
When configuring an LVDS SerDes receiver, is it necessary to meet the tREFPJ specification?
Stratix 10 also includes an LVDS SerDes, but this parameter is not listed in its documentation.

2. Interpretation of tREFPJ
Is it correct to understand tREFPJ as the integrated phase noise power spectral density of the CLK(LVDS) over the frequency range of 10 kHz to 50 MHz?

Thank you for your support.