Forum Discussion
3 Replies
- WZ2
Frequent Contributor
Hi there,
- Your understanding is correct.
- Do you happen to know the value of tREFPJ for the DS90CR481?
- Have you observed any noticeable data loss or mis-decoding? Typically, a 100 MHz accompanying clock is not considered a very stringent condition.
Best regards,
WZ
- kashi669266
New Contributor
I apologize for the unclear explanation. Please allow me to explain my concerns more clearly.
I’m assuming a circuit configuration as shown below:
I would like to ask about the following two points:1. Requirement for tREFPJ
When configuring an LVDS SerDes receiver, is it necessary to meet the tREFPJ specification?
Stratix 10 also includes an LVDS SerDes, but this parameter is not listed in its documentation.2. Interpretation of tREFPJ
Is it correct to understand tREFPJ as the integrated phase noise power spectral density of the CLK(LVDS) over the frequency range of 10 kHz to 50 MHz?Thank you for your support.
- kashi669266
New Contributor
Thank you for your response.
I appreciate your explanation. I am not very familiar with jitter theory, so your input was very helpful.
I do not know the value of tREFPJ for the DS90CR481.
We are still in the study phase, and no actual issues have occurred yet. However, I understand now that under the current conditions, there is little cause for concern.
Thank you again for your support.