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Hi guys,
Is anybody know the delay for AND2, OR2, NOT and D flip-flop based on the popular fabrication technique? and suppose the delay for an AND2 gate is unit 1, what about the delay for AND3 or AND4 under the same fabrication? I am talking about the propagation delays of gates within an IC.Thanks.
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The question has a different answer for every different type of technology.
- The answer for a CPLD will be different than the answer for an FPGA which will be different than the answer for an ASIC
- For a given technology, the answers can vary for different suppliers. For a given technology, the answer can vary by the process used by the same supplier to produce different generations of product
Kevin Jennings
Honored Contributor
