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Altera_Forum's avatar
Altera_Forum
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11 years ago

Question about optimizing a VHDL based system.

Hi all,

I finally managed to have my system to work as I expected but I am quite dissapointed with the too high number of LEs required by the entire project.

I wanted to know if you had books or websites that deal with optimization specifically.

I also wanted to know if reducing some bus size would reduce the number of LEs.

I have many 512 bits buses that I could probably break down into chunks of 32 bits by adding a "loading" process but I don't know if it will help.

By the way my project is open source so you can have a look at my sources and feel free to give me any tips regarding the coding style.

https://github.com/accpnt/sha1

Thanks for your answers.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    why such wide busses? couldnt you have pipelined the designed and put the data through rams?

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Have a look at the fitter compile report > Resource Section > Resource Utilization by Entity. There you can find out if one of your components stands out in resource usage or if it's a problem spread around your design.

    Large buses can lead to heavy resource usage, and usually 512-bit buses shouldn't be necessary if you don't need a huge data bandwidth. That said if all your logic operates on 512 bit words, serializing and deserializing them in 32-bit buses to interconnect several components together probably won't help much.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Hi,

    I've decided to reduce the bus sizes and I've managed to double the depth of my pipeline.

    I also want to put the largest registers in RAM but I don't really know how to do it.

    I've found the following doc : http://quartushelp.altera.com/12.1/mergedprojects/hdl/vhdl/vhdl_file_dir_ram.htm

    I followed the procedure like this :

    -- First, declare a signal that represents a RAM

    type memory_t is array (0 to 15) of std_logic_vector(31 downto 0);

    signal my_ram : memory_t;

    attribute ramstyle : string;

    attribute ramstyle of my_ram : signal is "M9K";

    But in the Fitter report it says that 0 M9K out of 66 have been used.

    Did I miss something ?

    Cheers,