Question about optimizing a VHDL based system.

Hi,

I've decided to reduce the bus sizes and I've managed to double the depth of my pipeline.

I also want to put the largest registers in RAM but I don't really know how to do it.

I've found the following doc : http://quartushelp.altera.com/12.1/mergedprojects/hdl/vhdl/vhdl_file_dir_ram.htm

I followed the procedure like this :

-- First, declare a signal that represents a RAM

type memory_t is array (0 to 15) of std_logic_vector(31 downto 0);

signal my_ram : memory_t;

attribute ramstyle : string;

attribute ramstyle of my_ram : signal is "M9K";

But in the Fitter report it says that 0 M9K out of 66 have been used.

Did I miss something ?

Cheers,