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Altera_Forum
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11 years ago

Question about optimizing a VHDL based system.

Hi all, I finally managed to have my system to work as I expected but I am quite dissapointed with the too high number of LEs required by the entire project. I wanted to know if you had ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

that is a very small memory. Also, you need to ensure your my_ram signal actually behaves like a ram - otherwise you cannot create one. The ramstyle attribute means nothing if it doesnt infer a ram.

Refer to the HDL coding guidelines for hardware inference

http://www.altera.co.uk/literature/hb/qts/qts_qii51007.pdf