Question about optimizing a VHDL based system.

Have a look at the fitter compile report > Resource Section > Resource Utilization by Entity. There you can find out if one of your components stands out in resource usage or if it's a problem spread around your design.

Large buses can lead to heavy resource usage, and usually 512-bit buses shouldn't be necessary if you don't need a huge data bandwidth. That said if all your logic operates on 512 bit words, serializing and deserializing them in 32-bit buses to interconnect several components together probably won't help much.