Altera_ForumHonored Contributor11 years agoQuestion about optimizing a VHDL based system. Hi all, I finally managed to have my system to work as I expected but I am quite dissapointed with the too high number of LEs required by the entire project. I wanted to know if you had ...Show More
Altera_ForumHonored Contributor11 years agowhy such wide busses? couldnt you have pipelined the designed and put the data through rams?
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