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Altera_Forum's avatar
Altera_Forum
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12 years ago

Question about optimizing a VHDL based system.

Hi all, I finally managed to have my system to work as I expected but I am quite dissapointed with the too high number of LEs required by the entire project. I wanted to know if you had ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

why such wide busses? couldnt you have pipelined the designed and put the data through rams?