Question about Monitor

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What you have told sounds exciting!! How do I measure the power dissipated on the board?

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If you have a board with current sensors, then you read the current sensors :)

If you don't then you can do it this way;

1) Power your board from a supply that you can measure the current, eg., replace a 12V wall-wart with a bench-top power supply, or cut the wires and put an ammeter in series with the supply wire.

2) Download a design that uses 'some' power, and measure the current when its operating.

3) Download another design that uses 'more' power, and measure the current when its operating.

4) See if the difference between the power measured in (3) and (2) is equivalent to the different predicted by Altera's tool.

Note that before you compare currents, you will have to translate your Quartus predicted FPGA supply rail currents into input power supply load current. To do this, you'll have to look at the power supply design and see whether the power supplies are linear (the input current is the same as the FPGA rail current) or switch-mode (the input current is less than the FPGA rail current by the ratio of voltages and efficiency, eg. 1.2A@1A = 12V@ 1Ax1.2V/12V/0.85 = 12V@0.12A for 85% conversion efficiency).

Cheers,

Dave

Good Morning Dave,

I have a master BFM connected to the slave port of the PCIe core [core one]. This core is connected to the master target memory. Can I write data to the target memory using API calls to the master BFM.[ through this call I want to control the core one. And using core one I want to control the target ]. Similar to PCIe BFM design you sent me

Thanks.

Aditya

Hi Aditya,

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I have a master BFM connected to the slave port of the PCIe core [core one]. This core is connected to the master target memory. Can I write data to the target memory using API calls to the master BFM.

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Where is this memory again? In the testbench PCIe master, or in the PCIe slave device? Either way, your Avalon-MM BFM in the master should be able to write to it. Eg., if the RAM is in the testbench PCIe master, then the Avalon-MM BFM can simply write to the address of the RAM. However, if the RAM is in the PCIe slave device, then the Avalon-BFM master in the PCIe master core first has to setup the PCIe master and then the PCIe slave interfaces.

PCIe traffic generally undergoes an address translation, and these are the registers you need to setup. For example, lets say the address map of your PCIe master design has an address decode to generate bus transactions setup at Avalon-MM address 0x1000_0000 in the master design. Any access by the Avalon-MM BFM master in the first design to this address will generate traffic on the PCIe bus. The packet that gets transmitted on the PCIe bus may have the same address, or it may have a translated address, lets say it gets translated to 0x2000_0000. If the PCIe slave has a BAR setup to respond to accesses to PCIe address 0x2000_0000, then it will accept that address. The PCIe slave may then implement address translation, eg. lets say it converts the MSBs of the address so that the translated addresses start at 0x3000_0000. The PCIe slave will then initiate an Avalon-MM transaction at address 0x3000_0000 in the slave device memory map. If the slave RAM is located at that address, then your Avalon-MM master back in the first design will successfully access the RAM in the second design.

The key thing to understand is the address mapping.

Cheers,

Dave

(Note: I assume this is how it works for PCIe, as this is how things work for PCI).

Good Morning Dave,

Thanks!. Is there a way to switch of the "Trimming" in Quartus. The software automatically trims all pins that does not have a fan out. Can I tell the software not to do this. I tried setting the pins to virtual pins but it did not help. [Also, I could not get all the pins listed].

Thanks,

Aditya

Hi Aditya,

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Is there a way to switch of the "Trimming" in Quartus. The software automatically trims all pins that does not have a fan out. Can I tell the software not to do this. I tried setting the pins to virtual pins but it did not help. [Also, I could not get all the pins listed].

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I'm not sure what you are talking about. Could you provide an example of pins that you would like to keep that are getting removed.

Perhaps the synthesis 'keep' directive is what you need?

http://quartushelp.altera.com/11.0/master.htm#mergedprojects/hdl/vlog/vlog_file_dir_keep.htm

http://quartushelp.altera.com/11.0/master.htm#mergedprojects/hdl/vhdl/vhdl_file_dir_keep.htm

Cheers,

Dave

Hello Dave,

Can I assign virtual pins to bidirectional pins. I am getting a Critical Warning "No exact pin location assignment(s) for 37 pins of 43 pins". In my .qsf file I have assigned all of these pins as virtual pins [and all these pins are Bidirectional].

Thanks and enjoy the weekend

Aditya

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Can I assign virtual pins to bidirectional pins.

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Why would you want to? If they are attached to physical pins, they will not get removed by synthesis.

Cheers,

Dave

Hello Dave,

How will I know if they are attached to physical pins? It is my own module. This module is a sub-module and only the clock pins go all the way to the top. This module has some ports that connect the other modules. For some reason, the bidirectional pins get assigned to a random pins. The input pins and output pins can be declared as virtual pins, but I have problem assigning the bidirectional ones.

When I look at the pin planner, I don't see these pins having any particular pin location !?!! However the pin location is shown in the Fitter synthesis report. I don't know what's going on[wrong].

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How will I know if they are attached to physical pins? It is my own module.

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Don't call them pins then. If they are the signals at the top-level of the component, they would be called ports.

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This module is a sub-module and only the clock pins go all the way to the top. This module has some ports that connect the other modules. For some reason, the bidirectional pins get assigned to a random pins. The input pins and output pins can be declared as virtual pins, but I have problem assigning the bidirectional ones.

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Huh? This makes no sense. You cannot have only the clock pins going to the top module, and then talk about bidirectional pins getting connected. What bidirectional pins? You just stated there were only clocks!?

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When I look at the pin planner, I don't see these pins having any particular pin location !?!! However the pin location is shown in the Fitter synthesis report. I don't know what's going on[wrong].

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The only thing that should connect to pins on the FPGA are ports on the top-level entity.

Please try to clarify what you are doing.

I know its confusing, but it helps if you are clear on what is wrong.

Cheers,

Dave

Good Morning Dave,

Oops sorry! I made that mistake again [confusing pins and ports]. I have a module [Lets call it module a]. "module a" has the following pins:

a) Clock Pins [6 in number]. [I want to assign them to the ports on FPGA]

b) Few Bidirectional Pins [37 in number].

c) Output pins[20 in number].

d) Input pins.[39 in number]

[I want to make b,c and d virtual]

I have assigned "a" to ports on the FPGA and in the .qsf file I have made b,c and d virtual. [Now, I expect to see "a" in the Pin Planner assigned to ports on the FPGA [I can see them]. I don't expect "b,c and d" to show up in the Pin Planner [I don't see them].

What is causing my confusion?

After compilation, the "Fitter Summary" says,

Total Pins: 43/307[14%]. [37 of them are not being assigned as Virtual Pins]

Total Virtual Pins: 59.

Additional Information:

1. In the ".qsf" file, except for "a" all are virtual.

2. In the Pin Planner, I can see 6 ports corresponding to "a"

]3. When I look at the "Input Pins" in the "Resource Section" I can see 6 clock Pins and each of them are associated with a unique "Pin#"

4. When I look at the "Bidir Pins" in the "Resource Section" I can see 37 Bidirectional Pins assigned to a unique "Pin#" [eg. K10, M7]

I shouldn't be seeing the ones in Red right?