Question about Monitor

Good Morning Dave,

Oops sorry! I made that mistake again [confusing pins and ports]. I have a module [Lets call it module a]. "module a" has the following pins:

a) Clock Pins [6 in number]. [I want to assign them to the ports on FPGA]

b) Few Bidirectional Pins [37 in number].

c) Output pins[20 in number].

d) Input pins.[39 in number]

[I want to make b,c and d virtual]

I have assigned "a" to ports on the FPGA and in the .qsf file I have made b,c and d virtual. [Now, I expect to see "a" in the Pin Planner assigned to ports on the FPGA [I can see them]. I don't expect "b,c and d" to show up in the Pin Planner [I don't see them].

What is causing my confusion?

After compilation, the "Fitter Summary" says,

Total Pins: 43/307[14%]. [37 of them are not being assigned as Virtual Pins]

Total Virtual Pins: 59.

Additional Information:

1. In the ".qsf" file, except for "a" all are virtual.

2. In the Pin Planner, I can see 6 ports corresponding to "a"

]3. When I look at the "Input Pins" in the "Resource Section" I can see 6 clock Pins and each of them are associated with a unique "Pin#"

4. When I look at the "Bidir Pins" in the "Resource Section" I can see 37 Bidirectional Pins assigned to a unique "Pin#" [eg. K10, M7]

I shouldn't be seeing the ones in Red right?