Question about Monitor

Hi Aditya,

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I have a master BFM connected to the slave port of the PCIe core [core one]. This core is connected to the master target memory. Can I write data to the target memory using API calls to the master BFM.

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Where is this memory again? In the testbench PCIe master, or in the PCIe slave device? Either way, your Avalon-MM BFM in the master should be able to write to it. Eg., if the RAM is in the testbench PCIe master, then the Avalon-MM BFM can simply write to the address of the RAM. However, if the RAM is in the PCIe slave device, then the Avalon-BFM master in the PCIe master core first has to setup the PCIe master and then the PCIe slave interfaces.

PCIe traffic generally undergoes an address translation, and these are the registers you need to setup. For example, lets say the address map of your PCIe master design has an address decode to generate bus transactions setup at Avalon-MM address 0x1000_0000 in the master design. Any access by the Avalon-MM BFM master in the first design to this address will generate traffic on the PCIe bus. The packet that gets transmitted on the PCIe bus may have the same address, or it may have a translated address, lets say it gets translated to 0x2000_0000. If the PCIe slave has a BAR setup to respond to accesses to PCIe address 0x2000_0000, then it will accept that address. The PCIe slave may then implement address translation, eg. lets say it converts the MSBs of the address so that the translated addresses start at 0x3000_0000. The PCIe slave will then initiate an Avalon-MM transaction at address 0x3000_0000 in the slave device memory map. If the slave RAM is located at that address, then your Avalon-MM master back in the first design will successfully access the RAM in the second design.

The key thing to understand is the address mapping.

Cheers,

Dave

(Note: I assume this is how it works for PCIe, as this is how things work for PCI).