Hello, is it possible to synthesize the "monitors" on the altera fpgas'. There are Monitor IPs such as Avalon MM Monitor. Can I synthesize such "Monitors"?

--- Quote Start --- is it possible to synthesize the "monitors" on the altera fpgas'. There are Monitor IPs such as Avalon MM Monitor. Can I synthesize such "Monitors"? --- Quote End --- No. The monitors are there to generate assertion messages regarding Avalon-MM bus protocol violations. Cheers, Dave

Thanks Dave. I came across some papers which discussed about developing monitors in SVA [System Verilog Assertion Language] and it stated that these monitors can be synthesized. "This paper presents one implementation of the Open Control Protocol (OCP) monitoring on the synthesized FPGA design using the implemented library of Synthesizable SystemVerilog Assertions (SSVA). The SSVA library is developed using the layer structure of SystemVerilog assertions. It is used in implementation of the monitors for two profiles of the OCP. SSVA library and OCP monitors are then functionally verified in simulator using the test case of the processor-memory communication. The test case is then synthesized on CHIPit Platinum Edition FPGA. The implemented library and monitors can be used in many commercial and educational projects due to their simplicity and low FPGA area usage."

--- Quote Start --- I came across some papers which discussed about developing monitors in SVA [System Verilog Assertion Language] and it stated that these monitors can be synthesized. --- Quote End --- Have a look at the source code. I think you'll find it wrapped in synthesis off/on blocks so that Quartus never even sees the code. That's certainly the case for the Avalon-MM master BFM component. The complication regarding synthesized assertions, is that an assertion needs some method of reporting failures, so a synthesizeable assertion checker would need an Avalon-MM interface with a block of control/status registers so that you could check for assertion failures, and clear error counters. But if your transaction just locked up the Avalon-MM bus, how would you read that register? You really don't want your transactions to fail in real hardware. That is what verification testing is for in the simulator :) Cheers, Dave

Monitors can be synthesized but not recommended right?. I will do some reading and get back to you about this. I have just started Qsys a few weeks ago, apart from the tutorials provided by qsys are there any other online tutorials/ good books about qsys. Thank you, Aditya

--- Quote Start --- Monitors can be synthesized but not recommended right? --- Quote End --- You're missing the point. The task of a monitor is to confirm that components adhere to the bus protocol specification. If a component will violate the bus specification, then its likely the bus will lock-up, and your system will freeze. Sure you can have a watch-dog reset the bus, and perhaps have a 'reset reason' and a backtrace. But all this can be reproduced in the simulation much easier. You setup randomized bus transactions, and code coverage, etc., and make sure things are well tested. Then you can synthesize. --- Quote Start --- I will do some reading and get back to you about this. --- Quote End --- Sure. I'm not saying they don't exist, but the question is what use are they? Feel free to come up with a good reason :) --- Quote Start --- I have just started Qsys a few weeks ago, apart from the tutorials provided by qsys are there any other online tutorials/ good books about qsys. --- Quote End --- You will learn best by building components, constructing _hw.tcl files, and synthesizing them. The nice thing about this approach is that you can get Quartus to generate an _hw.tcl file for some simple components, and then read the documentation about the settings. Things will make much more sense then. The Quartus handbook has chapters on Qsys. I think alot of the component stuff is the same as the SOPC Builder stuff, so you can look at that manual too. The Qsys tutorial has layers of hierarchy, since Altera wants to show off the new features of Qsys relative to SOPC Builder. Rather than using that to learn from, try to create a design with an Avalon-MM BFM master, and an Avalon-MM slave registers interface; don't use the PIO core, write your own. Then write a SystemVerilog testbench to generate read/write transactions to your registers. You can add an Avalon-MM monitor into your testbench, and then generate transactions that violate the bus specification, eg. perform a read or write with invalid byte enables and see the assertion failure messages. You must have a tool that supports System Verilog Assertions (SVA), like the full version of Modelsim, otherwise you will not get the SVA messages. Cheers, Dave

Question about Monitor | Altera Community

117 Replies

Altera_Forum
Honored Contributor
15 years ago
Thanks :-)
Altera_Forum
Honored Contributor
15 years ago
Hi Aditya,

--- Quote Start ---

Is my problem still unclear? Should I re-frame my question?

--- Quote End ---
Sorry for the delay in responding, I'm traveling, and only have sporadic internet access.

Its not clear to me why you want to use virtual pins. I have never found a need to use them. Its quite possible that the problems you are having are related to trying to use a feature for other than it was intended.

Rather than use bidirectional signals in components, you should use three ports; data_out, data_in, and data_oe, and then at the top-level design, use these three signals to implement a tri-state bus. Since these three signals (or ports) are unidirectional, you should be able to make them virtual.

Note, these unidirectional ports/signals can be connected to 'fake external devices' internal to the FPGA, where the fake devices can implement what you expect your external device to do. Using these fake devices, you can probably eliminate the need for virtual pins.

Cheers,
Dave
Altera_Forum
Honored Contributor
15 years ago
Thanks Rysc.
Altera_Forum
Honored Contributor
15 years ago
There are no internal tri-states. Synthesis can sometimes recode bidirectionals into muxing logic, assuming the solution is obvious. It's generally advised to avoid internal tri-states, since they don't really exist in hardware.
Altera_Forum
Honored Contributor
15 years ago
So, if a module [let this be sub-module that connects other modules] has "bidirectional pins" do they automatically get a pin location on the FPGA? What if I want to use the bidirectional pins to connect other modules?
Altera_Forum
Honored Contributor
15 years ago
I'm guessing bidirectional pins can't be virtual. A virtual pin routes inside the FPGA and never goes to an I/O. A bidir has a tri-state component that only exists in the I/O. I'm not sure how that would be virtual unless the tri-state was ripped out. I'm guessing the virtual assignment is ignored for those I/O.
Altera_Forum
Honored Contributor
15 years ago
Hello Dave,

Is my problem still unclear? Should I re-frame my question?

Thanks,
Aditya
Altera_Forum
Honored Contributor
15 years ago
Good Morning Dave,

Oops sorry! I made that mistake again [confusing pins and ports]. I have a module [Lets call it module a]. "module a" has the following pins:

a) Clock Pins [6 in number]. [I want to assign them to the ports on FPGA]
b) Few Bidirectional Pins [37 in number].
c) Output pins[20 in number].
d) Input pins.[39 in number]
[I want to make b,c and d virtual]

I have assigned "a" to ports on the FPGA and in the .qsf file I have made b,c and d virtual. [Now, I expect to see "a" in the Pin Planner assigned to ports on the FPGA [I can see them]. I don't expect "b,c and d" to show up in the Pin Planner [I don't see them].

What is causing my confusion?

After compilation, the "Fitter Summary" says,
Total Pins: 43/307[14%]. [37 of them are not being assigned as Virtual Pins]
Total Virtual Pins: 59.

Additional Information:

1. In the ".qsf" file, except for "a" all are virtual.
2. In the Pin Planner, I can see 6 ports corresponding to "a"
]3. When I look at the "Input Pins" in the "Resource Section" I can see 6 clock Pins and each of them are associated with a unique "Pin#"
4. When I look at the "Bidir Pins" in the "Resource Section" I can see 37 Bidirectional Pins assigned to a unique "Pin#" [eg. K10, M7]

I shouldn't be seeing the ones in Red right?
Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---

How will I know if they are attached to physical pins? It is my own module.

--- Quote End ---
Don't call them pins then. If they are the signals at the top-level of the component, they would be called ports.

--- Quote Start ---

This module is a sub-module and only the clock pins go all the way to the top. This module has some ports that connect the other modules. For some reason, the bidirectional pins get assigned to a random pins. The input pins and output pins can be declared as virtual pins, but I have problem assigning the bidirectional ones.

--- Quote End ---
Huh? This makes no sense. You cannot have only the clock pins going to the top module, and then talk about bidirectional pins getting connected. What bidirectional pins? You just stated there were only clocks!?

--- Quote Start ---

When I look at the pin planner, I don't see these pins having any particular pin location !?!! However the pin location is shown in the Fitter synthesis report. I don't know what's going on[wrong].
--- Quote End ---
The only thing that should connect to pins on the FPGA are ports on the top-level entity.

Please try to clarify what you are doing.

I know its confusing, but it helps if you are clear on what is wrong.

Cheers,
Dave
Altera_Forum
Honored Contributor
15 years ago
Hello Dave,

How will I know if they are attached to physical pins? It is my own module. This module is a sub-module and only the clock pins go all the way to the top. This module has some ports that connect the other modules. For some reason, the bidirectional pins get assigned to a random pins. The input pins and output pins can be declared as virtual pins, but I have problem assigning the bidirectional ones.

When I look at the pin planner, I don't see these pins having any particular pin location !?!! However the pin location is shown in the Fitter synthesis report. I don't know what's going on[wrong].

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Question about Monitor

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