Hello, is it possible to synthesize the "monitors" on the altera fpgas'. There are Monitor IPs such as Avalon MM Monitor. Can I synthesize such "Monitors"?

--- Quote Start --- is it possible to synthesize the "monitors" on the altera fpgas'. There are Monitor IPs such as Avalon MM Monitor. Can I synthesize such "Monitors"? --- Quote End --- No. The monitors are there to generate assertion messages regarding Avalon-MM bus protocol violations. Cheers, Dave

Thanks Dave. I came across some papers which discussed about developing monitors in SVA [System Verilog Assertion Language] and it stated that these monitors can be synthesized. "This paper presents one implementation of the Open Control Protocol (OCP) monitoring on the synthesized FPGA design using the implemented library of Synthesizable SystemVerilog Assertions (SSVA). The SSVA library is developed using the layer structure of SystemVerilog assertions. It is used in implementation of the monitors for two profiles of the OCP. SSVA library and OCP monitors are then functionally verified in simulator using the test case of the processor-memory communication. The test case is then synthesized on CHIPit Platinum Edition FPGA. The implemented library and monitors can be used in many commercial and educational projects due to their simplicity and low FPGA area usage."

--- Quote Start --- I came across some papers which discussed about developing monitors in SVA [System Verilog Assertion Language] and it stated that these monitors can be synthesized. --- Quote End --- Have a look at the source code. I think you'll find it wrapped in synthesis off/on blocks so that Quartus never even sees the code. That's certainly the case for the Avalon-MM master BFM component. The complication regarding synthesized assertions, is that an assertion needs some method of reporting failures, so a synthesizeable assertion checker would need an Avalon-MM interface with a block of control/status registers so that you could check for assertion failures, and clear error counters. But if your transaction just locked up the Avalon-MM bus, how would you read that register? You really don't want your transactions to fail in real hardware. That is what verification testing is for in the simulator :) Cheers, Dave

Monitors can be synthesized but not recommended right?. I will do some reading and get back to you about this. I have just started Qsys a few weeks ago, apart from the tutorials provided by qsys are there any other online tutorials/ good books about qsys. Thank you, Aditya

--- Quote Start --- Monitors can be synthesized but not recommended right? --- Quote End --- You're missing the point. The task of a monitor is to confirm that components adhere to the bus protocol specification. If a component will violate the bus specification, then its likely the bus will lock-up, and your system will freeze. Sure you can have a watch-dog reset the bus, and perhaps have a 'reset reason' and a backtrace. But all this can be reproduced in the simulation much easier. You setup randomized bus transactions, and code coverage, etc., and make sure things are well tested. Then you can synthesize. --- Quote Start --- I will do some reading and get back to you about this. --- Quote End --- Sure. I'm not saying they don't exist, but the question is what use are they? Feel free to come up with a good reason :) --- Quote Start --- I have just started Qsys a few weeks ago, apart from the tutorials provided by qsys are there any other online tutorials/ good books about qsys. --- Quote End --- You will learn best by building components, constructing _hw.tcl files, and synthesizing them. The nice thing about this approach is that you can get Quartus to generate an _hw.tcl file for some simple components, and then read the documentation about the settings. Things will make much more sense then. The Quartus handbook has chapters on Qsys. I think alot of the component stuff is the same as the SOPC Builder stuff, so you can look at that manual too. The Qsys tutorial has layers of hierarchy, since Altera wants to show off the new features of Qsys relative to SOPC Builder. Rather than using that to learn from, try to create a design with an Avalon-MM BFM master, and an Avalon-MM slave registers interface; don't use the PIO core, write your own. Then write a SystemVerilog testbench to generate read/write transactions to your registers. You can add an Avalon-MM monitor into your testbench, and then generate transactions that violate the bus specification, eg. perform a read or write with invalid byte enables and see the assertion failure messages. You must have a tool that supports System Verilog Assertions (SVA), like the full version of Modelsim, otherwise you will not get the SVA messages. Cheers, Dave

Question about Monitor | Altera Community

117 Replies

Altera_Forum
Honored Contributor
15 years ago
Hello Dave,

I have a Total Negative Slack of 1646 [reduced from 17000 after adding pipeline stages in Qsys]. I have reached maximum pipeline and cannot go any further.

The Latch clock and the Launch clocks are the same. How do I solve this problem without using "set_false_path" [This basically does tells TQA not to analyse that particular path and does not solve the problem right?]

I can get rid of this error by adding "set_multicyle_path" and relaxing the timing, but is this the right way?

And also I don't get a right estimate of the Fmax unless I use the right timing exceptions right?

Addition to Above Post:

I have found that the failing path is between within the Nios and there is a huge combinational logic between the input and output.

Thanks,
Aditya
Altera_Forum
Honored Contributor
15 years ago
Look at:
http://www.altera.com/literature/hb/nios2/edh_ed51007.pdf

You're probably well beyond what can be done in Quartus/TimeQuest. You have a design and with all the options switched it only runs so fast due to lots of logic. You may need to optimize the design. (And note that designs only run fast, so you're requirement may be too high for your design...)
Altera_Forum
Honored Contributor
15 years ago
Thanks I will take a look at it. Does this manual hold good for Qsys also?
Altera_Forum
Honored Contributor
15 years ago
Yes. (I'm not sure if it's 100% 1:1, but the principles are the same, and it shoudl be very close)
Altera_Forum
Honored Contributor
15 years ago
I can get rid of this error by adding "set_multicyle_path" and relax the timing, but is this the right way?
Altera_Forum
Honored Contributor
15 years ago
No. Never add multicycles to someone else's code(i.e. IP) unless you're certain it was designed to be a multicycle. Most likely it is real and is a real problem.
Altera_Forum
Honored Contributor
15 years ago
So, "set_multicycle_path" is not a "timing relaxation tool" and should be only used if the design actually has multicycle setup right?.

And if a Path has two cloks of different frequencies [if this difference is INTEGER multiple then it becomes "multicycle" right?] then i can consider these clocks a asynchronous and i can either set this path is "false path" or " separate those two clocks using "set_clock_group -asynchronous" [each clock will be in different groups] right?

Thanks,
AA
Altera_Forum
Honored Contributor
15 years ago
I'm not sure what a "timing relaxation tool" is? If the period is 10ns and the setup is 10ns, then that's what it needs to meet. If you're design runs where it sends data every other clock cycle or something like that, then two multicycles can be added to make it a 20ns setup and 0ns hold.
For paths between clocks, false paths are valid if your design treats it asynchronously. For example, you might have two 10ns clocks with data going between them through an asynchronous FIFO. That would allow you to cut timing between them. If you pass data directly and need it to get there in a cycle, then you can't cut timing. Obviously if the clocks are truly asynchronous, there is no way to pass data synchronously regardless of what your design expects, so the false path needs to be there and the design needs to handle the asynchronous nature. But multicycles and false paths are telling TimeQuest "what you designed for".
Altera_Forum
Honored Contributor
15 years ago
Thanks that clears some of my doubts.
Altera_Forum
Honored Contributor
15 years ago
what do you mean by "if your design treats it asynchronously" ?

"you might have two 10ns clocks with data going between them through an asynchronous FIFO. That would allow you to cut timing between them" [now if I set false path between the two clocks then about about other places where these two clocks are used ? (I am not able to visualize the problem)

can you explain "Obviously if the clocks are truly asynchronous, there is no way to pass data synchronously"

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