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Altera_Forum's avatar
Altera_Forum
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15 years ago

Question about Monitor

Hello, is it possible to synthesize the "monitors" on the altera fpgas'. There are Monitor IPs such as Avalon MM Monitor. Can I synthesize such "Monitors"?
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

what do you mean by "if your design treats it asynchronously" ?

"you might have two 10ns clocks with data going between them through an asynchronous FIFO. That would allow you to cut timing between them" [now if I set false path between the two clocks then about about other places where these two clocks are used ? (I am not able to visualize the problem)

can you explain "Obviously if the clocks are truly asynchronous, there is no way to pass data synchronously"