Forum Discussion
Honored ContributorQuestion about Monitor
Hello,
is it possible to synthesize the "monitors" on the altera fpgas'. There are Monitor IPs such as Avalon MM Monitor. Can I synthesize such "Monitors"?117 Replies
Altera_ForumI am having a similar issue where I need to simulate a PCIe design where the testbench should represent the stimulus as depicted by the PC. Any recommendations of where to start? and did you use the Altera Hard IP or Soft IP blocks.
Thank you in advance.- Altera_Forum
Hello Rysc,
In your timing analysis guide on page 32, I am not able to understand the sentence "Hold relationship means the data should get there after the latch clocks 0ns edge gets there" [2 line of the page] Thanks, AA - Altera_Forum
Hello Rysc and Dave,
Did I ask an invalid question? :-o Thanks, AA - Altera_Forum
Hello,
I have a system built in SOPC. Here is some background: 1. sopc: Timing Requirement met. 2. qsys: Timing Requirement not met even with 4 pipeline stages + I have followed the suggestions of Timing Optimization Advisor. [Timing error exists within NIOS component]. My Questions: 1. Apart from redesigning the system what are the other things I can do? 2. Does creating the Qsys system from scratch [rather than just upgrading the SOPC system] have any effect on the timing ? [I noticed that the Total Negative slack reduced when I built the system from scratch] Thanks, AA - Altera_Forum
Okay. Thanks.
- Altera_Forum
You just constrain the clocks, and all downstream logic should get constrained. You might need to add false paths between clocks(can use set_clock_groups to do this). You should not be adding any false paths or multicycles directly to paths in the avalon switch fabric.
- Altera_Forum
Rysc, usually I get timing errors between nodes that are related to the avalon switch fabric. How do I specify the timing constraints related to these nodes before I compile the design. [I will only know the errors after they are compiled] So in this case there is no other option other than specifying the timing exceptions in the sdc after the design right?.
I can specify the timing constraints before compilation, if it's my own design without any Avalon generated components, right? - Altera_Forum
what do you mean by "if your design treats it asynchronously" ?
"you might have two 10ns clocks with data going between them through an asynchronous FIFO. That would allow you to cut timing between them" [now if I set false path between the two clocks then about about other places where these two clocks are used ? (I am not able to visualize the problem) can you explain "Obviously if the clocks are truly asynchronous, there is no way to pass data synchronously" - Altera_Forum
Thanks that clears some of my doubts.
- Altera_Forum
I'm not sure what a "timing relaxation tool" is? If the period is 10ns and the setup is 10ns, then that's what it needs to meet. If you're design runs where it sends data every other clock cycle or something like that, then two multicycles can be added to make it a 20ns setup and 0ns hold.
For paths between clocks, false paths are valid if your design treats it asynchronously. For example, you might have two 10ns clocks with data going between them through an asynchronous FIFO. That would allow you to cut timing between them. If you pass data directly and need it to get there in a cycle, then you can't cut timing. Obviously if the clocks are truly asynchronous, there is no way to pass data synchronously regardless of what your design expects, so the false path needs to be there and the design needs to handle the asynchronous nature. But multicycles and false paths are telling TimeQuest "what you designed for".
